Sample SOC and Testbench
System with Multiple SOC’ s
Testbench Requirements
Stimulus Generation
Directed, Random, ATPG, …
Checkers
Data
Protocols
Structured Connection to Multiple Independent Interfaces
Interconnect
Clocking Domain
Protocol
Abstract Modeling
High-level data structures
Dynamic Memory
Memory Management
Re-entrant Processes
Inter-process Synchronization, Control, and Communication
Re-usability
Single language for design (HDL) and verification (HVL) HDVL
Basic Types
Strings
arbitrary and dynamic length
methods to manipulate and convert strings
operators for comparison, concatenation and replication
Associative arrays
Indexed by integer, string, or class
first(index), last(index), next(index), prev(index), delete(index), and exist(index) methods
Dynamic arrays
integer mem[*];
mem.size();
Linked Lists
doubly linked list of any data type
iterator, modification, access methods
Classes, Objects and Methods
Object Oriented
Encapsulation, Inheritance, and Polymorphism
Objects referenced with handles (Safe Pointers)
Random Variables and Constraints
Random Variables and Constraints
rand, randc, and constraint added to class definition
Basic Additions
Wild card operators (=?= and !?=)
Pass by reference
Argument default values and pass by name
Alias for nets
Short nets in a module
Dynamic Memory
Objects, threads, strings, dynamic and associative arrays
Automatically Managed
Process Control/Synchronization
Verilog thread support from fork join with continuation when all threads complete
SV threads use fork join with continuation control
all
any
none
Threads execute until a blocking statement
wait for event, mailbox, semaphore, variable change, …
Enhanced events (value and duration, passed as arguments)
Threads are controlled by
$terminate
$wait_child
$suspend_thread
$exit
Clocking Domain
Synchronous Interfaces: Clocking
Testbench Program Block
System Verilog Testbench